View mas31750 datasheet online:
HIGH PERFORMANCE MIL-STD-1750 MICROPROCESSOR
The GEC Plessey MA31750 is a single-chip The MA31750 has on-chip parity generation and checking
microprocessor that implements the full MIL-STD-1750A to enhance system integrity. A comprehensive built-in self-test
instruction set architecture, or Option 2 of Draft MIL-STD- has also been incorporated, allowing processor functionality to
1750B. The processor executes all mandatory instructions and be verified at any time.
many optional features are also included. Interrupts, fault Console operation is supported through a parallel interface
handling, memory expansion, Console, timers A and B, and using command/data registers in l/O space. Several discrete
their related optional instructions are also supported in full output signals are produced to minimise external logic.
accordance with MIL-STD-1750. Control signals are also provided to allow inclusion of the
The MA31750 offers a considerable performance increase MA31750 into a multiprocessor or DMA system.
over the existing MAS281. This is achieved by using a 32-bit The processor can directly access 64KWords of memory in
internal bus structure with a 24 x 24 bit multiplier and 32-bit full accordance with MIL-STD-1750A. This increases to
ALU. Other performance-enhancing features include a 32-bit 1MWord when used with the optional MA31751 memory
shift network, a multi-port register file and a dedicated address management unit (MMU). 1750B mode allows the system to
calculation unit. be expanded to 8MWord with the MMU.
Parity arb. Address Data
generator Microcode control
words to other blocks
Multiplier Shift network
Figure 1: Architecture
1. ARCHITECTURE 2. ADDITIONAL FEATURES
The GEC Plessey MA31750 Microprocessor is a high The MA31750 may be operated in one of two basic user
performance implementation of the MIL-STD-1750A (Notice 1) selectable mod